A Brief History of Semiconductor Packaging
发布时间 2023-04-02 23:00:28 来源
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In this video we're going to look at a brief history of the semiconductor packaging industry. Packaging refers to the integrated circuits, carrier, and enclosure. It protects the silicon die inside from physical damage while also allowing it to be connected to other devices. The industry has long been overlooked by the sexier work of wafer fabrication, but it's important and we should know about it. Let's go.
在这个视频中，我们将简要介绍半导体封装行业的历史。封装指的是集成电路、载体和外壳。它可以保护芯片内部的硅片免受物理损坏，同时还能将其连接到其他设备。封装行业长期以来一直被晶圆制造这样更有魅力的工作所忽视，但它是很重要的，我们应该了解它。让我们一起来看看。
But first let me talk about the agenometry Patreon. Early access members see new videos and selected references for them before the release of the public. They help support the videos and I appreciate every pledge. Thanks and on with the show.
首先让我来谈谈agenometry Patreon。早期接触会员在视频发布之前就能够看到新视频和为其选择的参考资料。他们帮助支持视频制作，我非常感激每一份赞助。谢谢大家，请继续收看本节目。
ICs are precious little snowflakes. They need protection from the real world, which is full of damaging influences. Particles can get in and interfere with operations. Moisture in the air can cause their metals to corrode. High temperatures generated during operations can cause the IC to degrade or even fail outright. Vibrations or jolts can damage the chip's capabilities and so on. The packaging is for protecting from all of these threats.
集成电路就像珍贵的小雪花。它们需要保护来抵御来自现实世界的众多危害。微小的粒子可能会进入并干扰操作。空气中的水分可能会导致金属腐蚀。在操作过程中产生的高温可能会导致集成电路逐渐退化或直接失效。震动或冲击可能会损坏芯片的功能等等。包装就是为了保护电路免受所有这些威胁。
Let's talk about what's inside. First we have your die. The die attaches to a metal support called a lead frame, oftentimes through the use of clips, adhesive, or straps. The lead frame has wires attached to it, which connect it to the outside world. These are called bond wires. And then finally there is a plastic or ceramic or metal enclosure surrounding the die, the lead frame, and the bond wires. This whole setup is considered by the industry as only the first level of semiconductor packaging.
咱们来聊一下芯片内部的结构吧。首先是芯片本身，它会通过夹子、胶粘或者条带的方式与一个金属支架——引线架相连。引线架上面固定着连接外界的金属线，称为键合线。最终芯片、引线架和键合线都会被塑料、陶瓷或金属的外壳所包裹。整个结构被行业认为是半导体封装的第一层。
The second level refers to the circuit board, and the third and final level refers to the system's final enclosure, like the desktop PC's chassis. The process of encasing the fabricated die into its level 1 package is referred to as the back end. We can further break down back end processes to two major steps, assembly and test.
第二层指的是电路板，第三和最后一层指的是系统的最终外壳，就像台式电脑的机箱一样。将制造好的芯片封装到第一层包裹中的过程被称为后端。我们可以进一步将后端过程分为两个主要步骤：组装和测试。
Processes differ based on the technology, but here is the vanilla workflow. In assembly, we start by cutting the dies out of the completed wafer and inspecting them. After this we have to put the dies onto the packages lead frame called die attach or die bonding or die mounting. Then we attach the very small bond wires to the dies, which allow the chip to communicate with the outside world.
根据不同的技术，加工流程是不同的，但以下是基本工作流程。在组装中，我们首先将已成型的晶圆切割成芯片并进行检查。接着我们需要将芯片装置到被称作芯片焊接或芯片安装的封装铅架上。然后我们在芯片上连接非常细小的焊丝，以便芯片能与外界通信。
This step is called wire bonding and was pioneered by Bell Labs in the 1950s. After that we put the die into its ceramic or plastic package to protect it from the outside world. At the start this process had to be done manually, making it one of the first things to be outsourced abroad. Since then machines have taken over, and a swath of new bonding techniques have been introduced, discussing them is beyond the scope of this video, but you should know they exist.
这一步被称为线缆焊接，是由贝尔实验室在1950年代首创的。然后，我们将芯片放入它的陶瓷或塑料封装中，以保护它免受外界的影响。起初这个过程必须手动完成，因此成为最早被外包到国外的工序之一。此后，机器接替了人工，还引入了许多新的焊接技术，虽然本视频无法讨论它们的细节，但您应该知道它们的存在。
Throughout its history, packaging schools have stayed rather consistent, helped the IC achieve its full functionality and don't get in its way, be as small as possible, and be as cost-effective as possible. In the beginning, only military or aerospace companies used semiconductors. Price was less of a concern than total reliability. There go most semiconductor manufacturers, packaged their dies, in hermetically sealed cans made out of ceramic or steel. This prevented any contaminants from messing with the chip, but there were serious drawbacks.
在其历史上，封装学校一直保持相当一致，帮助集成电路实现其全部功能且不妨碍其进行。 封装体积尽可能小，并尽可能节省成本。 在最初阶段，只有军事或航空公司使用半导体。 价格不是最大的考虑因素，而是总可靠性。 因此，大多数半导体制造商将其芯片包装在由陶瓷或钢制成的密封罐中。 这样可以防止任何污染物对芯片的影响，但存在严重缺点。
Ceramics and metal cost a lot. They're also heavy, which meant that the circuit boards they were attached to had to support all that weight. This made them heavy too. Faire child semiconductor, when Faire child started producing their revolutionary planar ICs in the late 1950s, they packed them in the same T-O5 and flat pack packages they used for transistors, just with a few more leads. We will talk about flat packs a little later in this video, but first let us talk about the T-O5.
陶瓷和金属很昂贵，而且很重，这意味着它们连接的电路板必须承受所有的重量，从而使电路板变得很重。菲尔德半导体公司在上世纪50年代末开始生产他们的革命性平面集成电路时，使用与晶体管相同的T-O5和平面封装，只是带有更多的引线。我们稍后将在这个视频中讨论平面封装，但首先让我们谈谈T-O5。
The T-O stands for transistor outline. A T-O5 kind of looks like a squid, basically a metal can and metal lid. Faire child's first micrologic chips were accordingly etched in a round shape. But the T-O5's awkward round shape made it difficult to attach onto and arrange on a board, adding to the labor cost. Worse yet, T-O5's limited how much data the chip can take in and push out. They maxed out at just 8 to 10 pins, Faire child's new logic circuits needed far more than that.
T-O是晶体管外观的缩写，T-O5的外形有点像乌贼，基本上是金属罐和金属盖。Faire child的第一批微型逻辑芯片是按照圆形刻制的。但是，T-O5笨拙的圆形外形使其难以安装和排列在电路板上，增加了人力成本。更糟糕的是，T-O5芯片能够处理的数据量有限，只有8到10个针脚，而Faire child的新逻辑电路需要更多的针脚。
T-O5 packaging diluted the ICs advantages and worsened its disadvantages. With this situation, however, are ICs ever going to get to price parity with germanium devices and vacuum tubes. In response, Faire child developed two new packaging techniques. The first was plastic encapsulation. This sounds fancy, by the way, they did it back then was to put the IC die on a ceramic bead and cover the whole thing with a plastic blob. This method had some issues.
T-O5包装削弱了IC的优势并加剧了其劣势。然而，在这种情况下，IC是否能够达到与锗器件和真空管的价格平价。作为回应，Faire child发展了两种新的包装技术。第一种是塑料封装。顺便说一下，他们当时的方法是将IC芯片放在陶瓷珠上，然后用塑料块覆盖整个东西。这种方法存在一些问题。
Plastic can be permeable to certain chemicals leading to concern surrounding contamination. And plastic can shrink or grow depending on outside conditions like heat, inflicting mechanical stress on the chips inside. However, plopping plastic onto a chip required very little skill, this meant that Faire child circuit outsources assembly work to cheap manual labor in Hong Kong or South Korea. One of the first such electronics companies to do so.
塑料可能对某些化学物质具有渗透性，从而引起有关污染的担忧。而且，塑料可以根据外部条件（如热量）收缩或扩张，对芯片内部施加机械应力。然而，将塑料放在芯片上所需技能很少，这意味着Faire child circuit将组装工作外包给便宜的手工劳动力在香港或韩国。这是最早这样做的电子公司之一。
Faire child's second idea would forever change semiconductor packaging. Faire child's digital systems laboratory head, Rex Rice, created a new lead configuration for an IC. The leads were spaced about 100,000 of an inch apart. The industry term for this measurement is lead pitch and came out in a single line. You would attach the package to the circuit board using what is called through hole mounting.
费尔儿童的第二个想法将永远改变半导体封装。费尔儿童的数字系统实验室负责人雷克斯·莱斯为一个IC（集成电路）创建了一个新的引线配置。这些引线之间间隔约为100,000英寸。这种测量的行业术语称为引线间距，并呈单行排列。通过所谓的通孔安装，您可以将封装附加到电路板上。
Here, you insert the packages leads through literal holes drilled into the boards. The holes have large round solder contact areas surrounding them. After insertion, you solder the leads on the backside to secure them. The method for doing this was called wave soldering. Tests found that this new inline packaging system fit all the criteria. It can accommodate more IO, some 12-16 pins at the start. It simplified the circuit board layout, and finally it took less time and skill to assemble. The inline arrangement was far simpler than the T05 cans circle shaped leads.
在这里，您将通过直接钻在电路板上的实心孔将封装引线插入其中。孔口周围有着大圆形的焊接接触区域。插入引线后，你需要在背侧焊接以固定它们。这种方法被称为波峰焊。测试发现，这种新的直插式封装系统符合所有标准。它可以容纳更多的输入/输出，最初有12-16个引脚。它简化了电路板布局，最终组装所需的时间和技能也更少。而且，这种直插式排列要比T05罐形引线要简单得多。
Before deploying the product, Faire child first consulted with customers and end users, who did not like the single line arrangement. However, they would be okay with two lines. So Faire child revised the prototype to two rows of inline pins, dual inline packaging or DIP. Introduced in 1965, the simplicity of dual inline packaging cut the cost of assembly by a factor of 4. The industry widely adopted it throughout the 1970s and 80s. During those 20 years, DIPs, which includes ceramic and plastic versions, held some 80-90% market share when measured by value.
在部署该产品之前，Faire孩子首先与客户和最终用户进行了咨询，他们不喜欢单行排列的设计。不过，两行排列的设计还是可以接受的。因此，Faire孩子将原型改为两行内联针脚组件或DIP。DIP是在1965年引入的，其简单性使得组装成本降低了4倍。在整个70年代和80年代，该行业广泛采用了DIP，其中包括陶瓷和塑料版本，这20年间DIP占据了市场价值的80-90%。
However, as the industry moved into the 1970s and the era of very large scale integration or VLSI, demands for IO density kept growing. Some VLSI chips would require as many as 300 leads. More leads forced the DIPs to grow increasingly large. DIPs can have 64 or even more leads, but doing so gave them in practically large board footprints. If trends continued the way they were, the DIP packages would end up being far larger than the dies themselves. This invalidates the various miniaturization gains in semiconductor manufacturing.
然而，随着工业进入 1970 年代和大规模集成或 VLSI 时代，对 IO 密度的需求不断增加。一些 VLSI 芯片需要多达 300 条引线。更多的引线强迫 DIPs 变得越来越大。 DIPs 可以有 64 甚至更多的引线，但这样做实际上使它们的印刷板占用面积变得更大。如果继续按照现有趋势发展，DIP 封装会变得比芯片本身要大得多。这将使半导体制造越来越微型化的各种成果无效。
In response to this trend, a series of new packages capable of accommodating far more leads emerged, the packaging industry's second big revolution. This generation of packages was defined not by their shape, but rather how they were attached to the circuit board.
针对这一趋势，出现了一系列新的包装方案，能够容纳更多的引脚，这是包装行业的第二次大革命。这一代包装的定义并不是由它们的形状决定的，而是由它们连接电路板的方式决定的。
Surface mounting technology describes a style of mounting packages onto the board using flat patches of solder already on the board. Surface mounting had several advantages over through-hole mounting. First, because through-hole mounting required you to solder the backside of the boards to secure the DIPs, you can only use one side of the board. With surface mounting, you can use both. This alone increases the theoretical number of packages on a single board by 35 to 60%.
表面贴装技术指的是使用已经铺在电路板上的扁平焊锡垫将封装件固定在电路板上的一种技术。与插针式固定技术相比，表面贴装技术具有几个优点。首先，插针式固定技术需要将电路板背面焊接以固定DIP，只能使用电路板的一面。而表面贴装技术可以使用两侧，这一点单独就能增加单个电路板上理论封装数量的35至60%。
Second, it allowed us to move the leads closer together, or in other words, for a smaller lead pitch. This is because you no longer have the solder contact areas around the holes. And third, you can use cheaper boards, drilling a hole into a board costs money, and there can be up to a thousand holes on a standard board. Ray estimates found that a surface mount board costs 13 cents per square inch, while an insertion hole mounting board costs 15 cents. Furthermore, the boards aren't peppered with holes anymore, which means they don't need so many layers to maintain their structural integrity, another cost saving measure.
其次，这种表面安装技术使得元件引脚可以更接近，也就是说可以使用更小的引脚间距。由于不需要在孔周围设置焊接接触面积，这也成为可能。第三，你可以使用更便宜的电路板。在电路板上钻孔需要费用，标准电路板上可能有多达一千个孔。根据雷的估算，表面安装电路板每平方英寸的成本为13美分，而插孔安装电路板的成本为15美分。此外，电路板上不再遍布孔洞，这意味着它们不需要保持结构完整性的那么多层，这是另一项节约成本的措施。
Previously, all that surface mounting had to be done by hand, which, considering the smaller lead pitches, required a great deal of skill and training. This was the primary reason why surface mounting didn't take off at first. New automatic machines finally closed the loop on this. Manufacturers now use convection heating, hot gas, or even infrared heat rays to solder the packages onto the boards, basically ovens.
以前所有的表面贴装都需要靠手工完成，考虑到引脚距离更小，需要很高的技能和培训。这是为什么表面贴装一开始没有流行的主要原因。新的自动化设备最终解决了这个问题。制造商现在使用对流加热、热气体，甚至是红外辐射来将封装焊接到电路板上，基本上是烤箱。
The origins of modern surface mounting technology are murky, and there isn't one significant inventor or eureka moment. I mean the concept of attaching stuff to a board is not exactly groundbreaking. The earliest credible mention is a British patent filed in 1960. It describes resistors, coils, and such attached to a printed board using an adhesive. The connectors were connected using solder.
现代表面贴装技术的起源并不清楚，也没有一个显著的发明家或灵光一现的时刻。我指的是将东西粘贴到板上的概念并不是一件令人惊讶的事。 最早可信的提及是在1960年提交的英国专利中。它描述了电阻器、线圈等附着在印刷板上，使用粘合剂固定。 连接器使用的是焊料。
Early adopters in the 1960s included the US military, which used flat packs for their missile guidance computers. The flat pack was a stackable rectangular glass and ceramic package that was surface mounted onto a board. The flat pack was invented in 1962 by Young Tao of Texas Instruments, so actually a few years older than the venerable DIP. I couldn't find much more about inventor Young Tao or his life, which is unfortunate.
20世纪60年代，早期采用者包括美国军方，他们用平板包装来制作他们的导弹制导计算机。平板包装是一种可堆叠的矩形玻璃和陶瓷封装，可表面贴装于电路板上。平板包装是由德州仪器的Young Tao于1962年发明的，实际上比备受尊崇的双列直插包装（DIP）早了几年。我没有找到更多有关发明家Young Tao或他的生活的信息，这是不幸的。
In the late 1960s, a Swiss watch industry adopted surface mounting as a way to reduce some number of electronics in their watches. They popularized what is called the small outline integrated circuit, sometimes also known as the Swiss outline. The small outline looks like the DIP and is made from the same molded plastic materials. However, it is far smaller, a third is high and half as long. This was because as 28 gold wing leads are spaced far closer together, possible again, because we are directly mounting these onto the board. They are called gold wing leads because their shape is somewhat reminiscent of seagulls wings. Seagulls are birds that steal your hot dogs at the beach.
在1960年代后期，瑞士的手表工业采用表面贴装技术，以减少手表中的一些电子元件。他们推广了所谓的小封装集成电路，有时也被称为瑞士封装。 这种小型封装看起来像DIP，由相同的模塑料材料制成。 但是，它要小得多，高度只有三分之一，长度只有原来的一半。这是因为28个金色飞翼引线被更接近地排列在一起，这是因为我们直接将它们安装在电路板上。 它们被称为金色飞翼引线，因为它们的形状有些像海鸥的翅膀。 海鸥是在海滩上偷你热狗的鸟。
In the 1970s, the Japanese electronics industry began adopting surface mounting technology for their car radios, TV tuners and TV cameras. It is likely they got the idea from Europe, Germany or Britain perhaps. By the 1978 and 1980 period, the semiconductor packaging industry had started moving towards surface mounting, with numerous published articles discussing its use for increasing packing density.
在20世纪70年代，日本的电子业开始采用表面贴装技术生产汽车收音机、电视调谐器和电视摄像头。可能他们是从欧洲（可能是德国或英国）得到这个想法的。到了1978年和1980年期间，半导体封装业也开始采用表面贴装技术，许多发表的文章讨论了它在增加封装密度方面的应用。
In the early 1980s, the Japanese revived the old US military flat pack to create an updated surface mount compatible version called the Quad Flat Package or QFP. With the Quad Flat, we have the leads projecting down and away from all four sides of the square package. Depending on their size, the Quad Flat can offer anywhere from 20 to 240 leads. Pitches shrank to as small as 1 or 0.65 mm. You can go guess how many inches that is.
在20世纪80年代初，日本人使用美国旧款的军用扁平包装盒制造了一个更新的表面安装兼容版本，称为Quad Flat Package或QFP。在Quad Flat中，引线从正方形包装的四个侧面向下和向外延伸。根据它们的尺寸，Quad Flat可以提供20到240个引脚。间距缩小到1或0.65毫米。你可以猜测这是多少英寸。
简单来说，Quad Flat Package是一种更先进的表面安装电子元件包装形式，具有更多的引脚和更小的间距。这种尺寸小而灵敏的元件是现代电子产品中很重要的一部分。
The Quad Flat quickly evolved. Push along by consumer demands for smaller and smaller consumer electronics, the Japanese industries introduced yet smaller packages like the shrink quad flat package, the very small quad flat package and the thin quad flat package. On the other end of the spectrum, new structures outpaced the Quad Flat on the lead count front. People realized that having the leads come out of the sides meant that you couldn't use the real estate underneath the package itself.
四平贴片迅速演变。在消费者对越来越小的消费电子需求的推动下，日本工业推出了更小的封装，如缩小四平贴片、超小型四平贴片和薄型四平贴片。另一方面，新结构在引线数量方面超过了四平贴片。人们意识到，将引线从侧面引出意味着不能使用封装本身下面的空间。
So for high lead count devices, the packaging industry revived an old IBM invention, the pin grid array or the PGA. First introduced in 1971, the square shaped pin grid array can handle hundreds of leads on its underside. IBM invented the pin grid array for high IOUs in the computer industry. Those packages were made from ceramic, which not only made them more expensive, but also their circuit boards, since those boards had to get thicker to handle the added weight. Plastic variants were later introduced.
针对高引脚数的器件，包装行业重新启用了IBM的一个旧发明，即针脚阵列（PGA）。针脚阵列是一个正方形的器件，可以在其底部容纳数百个引脚。IBM为计算机行业中的高IOUs（输入/输出单元，即输入输出接口）发明了针脚阵列。这些封装是由陶瓷制成的，这使得它们更昂贵，并且它们的电路板也必须更厚，以处理额外的重量。后来又推出了塑料变种。
Pin grid arrays were invented before the surface mount revolution. So a surface mount compatible cousin emerged in the 1980s, the ball grid array. With these solder balls are used rather than pins to connect the chip to the circuit board. One big disadvantage of the ball grid was that you could not easily visually inspect the solder connections underneath the package. X-ray and electrical tests are often used instead with badly soldered packages removed, re-balled and re-applied. solder ball technology appear in another packaging innovation that popularized at about the same time as the BGA.
针状排列阵列是在表面贴装技术革命之前发明的。因此，在1980年代出现了一种与表面贴装兼容的亲戚，即球形排列阵列。 使用这些焊球而不是引脚将芯片连接到电路板。 球状排列的一个重大缺点是无法轻松地视觉检查包装下面的焊接连接。 X射线和电气测试通常被用来检测，有损坏的焊接包装被移除、重新焊球和重新应用。 焊球技术出现在另一个包装创新中，该创新约在BGA流行的同时出现。
Flip chip. This is where the silicon die is flipped, so that it faces downwards. To build the interconnects, we ditch wire bonding entirely and connect using bumps and balls on the chip's pads. Flip chip technology is still used today and offers several benefits. First, there is more contact with a heat sink, which dissipates more heat. Second, electrical signals have a shorter distance with flip chip interconnects than bond wires.
翻转芯片。这是将硅片翻转面对下方的技术。为了搭建互连，我们完全放弃了线键合技术，改用连接芯片接触点上的凸峰和球状物。翻转芯片技术仍在今天使用，并提供了几个好处。首先，与散热器的接触更紧密，可以散热更多热量。其次，翻转芯片互连的电信号传输距离比键合线要更短。
Starting in the 1990s, consumers started buying smaller electronics like mobile phones. Smaller devices mean smaller components, chips, and packages. Space became a premium in a chip package. The industry measures this using what is called packaging efficiency, the ratio of the area occupied by the active device, the die. In response to this, the packaging industry developed the chip scale package, which entered the market in the mid 1990s.
自1990年代起，消费者开始购买更小的电子产品，例如移动电话。较小的设备意味着组件、芯片和封装也更小。芯片封装中的空间成为了稀缺资源。行业已开始使用封装效率来衡量，即活动器件（晶圆）占据的面积与整个封装面积的比值。为了应对这种情况，封装行业于1990年代中期推出了芯片级封装，进入市场。
Chip scale packaging is an evolution of the aforementioned ball grid array, and refers to any package where the bear die occupies 80% or more of the total package area. Taiwanese OSAT vendors like ASC Group rose up on the back of such ultra compact packages. One prominent implementation of this concept is called wafer level packaging. This is where we hook up all the die interconnects before we cut those dies out of the wafer. It's not only very cost effective, but gives you very small packages.
芯片级封装技术是以上所提到的球栅阵列技术的升级版，指的是芯片占据总封装面积80%或以上的任何封装方式。像台湾OSAT供应商ASC Group这样的公司在这种极度紧凑的封装技术支持下崛起。其中一个重要的实现是称为晶圆级封装技术的封装方式。这是在我们对晶圆进行切割之前，将所有芯片之间的互连部分连接起来的技术。不仅成本非常经济实惠，而且包装体积也很小。
As I mentioned earlier, the advent of surface mounting technology created a new generation of packages and techniques. Has Moore's law slows down, packaging technologies have seen yet another surge of investment, creating what we can call advanced packaging solutions. These new packaging technologies now have a much more direct role to play in the systems overall performance.
正如我之前提到的，表面贴装技术的出现创造了一种新一代的封装和技术。随着摩尔定律的放缓，封装技术又经历了一波投资热潮，创造了我们可以称之为先进封装解决方案的技术。现在，这些新的封装技术在系统整体性能中扮演着更加直接的角色。
Semi-analysis has a fantastic multi-part breakdown on advanced packaging that I think drops the mic on the subject. Perhaps the most well known of these are chiplets. This is a variant of what are called multi-chip modules or hybrid circuits or system in packages. I did a video about it previously. Most prominently AMD used them to create a disruptively great product.
Semi-analysis对于先进封装进行了精彩的多部分分析，我认为这是该主题的走向巅峰。其中最广为人知的是chiplets。这是所谓的多芯片模块，混合电路或系统封装的变体。我之前曾经制作了一个有关它的视频。最值得一提的是，AMD使用它们来创造了一个具有颠覆性的伟大产品。
One special area of the multi-chip worlds involves 2.5D and 3D integration. These are especially cool. 2.5D integration is where we put multiple die side by side on top of an interconnect substrate called a silicon interposer. This silicon interposer doesn't have any logic, but is just made up of many embedded interconnects. There are a few consumer products using 2.5D integration today. For instance, AMD's Radeon R9 Fury GPU first introduced in 2015. As a name implies, 2.5D is an intermediate step towards 3D packaging, stacking and connecting multiple dies.
多芯片领域中一个特殊的领域涉及2.5D和3D集成。这些特别酷。2.5D集成是指将多个芯片并排放置在一个名为硅中间层的互联衬底上。这个硅中间层没有任何逻辑，只是由许多嵌入式互连构成。目前已经有一些消费品使用2.5D集成技术，例如AMD的Radeon R9 Fury GPU，该产品于2015年首次推出。正如其名称所示，2.5D是朝着3D封装、堆叠和连接多个芯片的中间步骤。
We are now able to use a whole new dimension to achieve packaging efficiencies of over 100%. Connecting these dies may require something more heavy than your standard wire bonds, bringing forth new concepts like the Thru Silicon Vias or TSVs. I am working on a future video on 3D integration and die stacking, so keep an eye out for that, if I ever finish it.
我们现在可以利用全新的维度来实现超过100%的包装效率。连接这些芯片可能需要比标准焊线更重的东西，引出新的概念，如晶圆穿孔或TSV。我正在制作一部关于三维集成和芯片堆叠的未来视频，请留意一下，如果我能完成它的话。
The semiconductor packaging industry is truly a chaotic one. There are so many different technology trees growing concurrently with one another, each branch developing and splitting for a certain significant need. New technologies are built on top of those addressing particular niche applications, and then suddenly before you know it, you have no idea why this new thing, which you saw fail a long time ago, is now such a big deal all over again.
半导体封装行业是一个真正混乱的行业。有很多不同的技术同时发展，每个分支分别为特定的重要需求发展和分裂。新技术建立在那些针对特定细分市场的技术之上，突然之间，你已经不知道为什么那个你很久以前看到它失败的新技术，现在又成为大头目了。
In the semiconductor packaging world, ideas are created and then vanish off the mainline, only to return to the forefront when their time is right. Love it. Expect more deep dives into semiconductor packaging in the near future, as we familiarize ourselves with this new world.
在半导体封装领域，创意时常冒出又消失，直到适合的时机才回到前台。这让人着迷。在不久的将来，我们将更加熟悉这个全新的世界，并深入研究半导体封装。